23rd IEEE European Test Symposium | May 28 - June 01, 2018 | Bremen, Germany
Special Session 1: Functional Safety and Test
Moderator: Daniel TILLE, Infineon Technologies - Germany
Infineon Technologies - Germany
From customer requirements to safe silicon development and test
Complexity and functionality of modern silicon-based systems (electronical and software components) are driven by new applications like "Advanced Driver
Assistant Systems" and "Autonomous Driving". These new applications rely on high quality in management, development and production of used components and
system integration. Therefore the demand on systematic processes and rules results in standardization like ISO 26262 "Road Vehicles-Functional safety".
This talk will demonstrate the adaptation of ISO 26262 into a silicon development process and provides insight how test and validation contributes to
Fraunhofer Institute - Germany
Functional Safety - challenges and chances
Functional safety has gained fast growing interest over the last decade. Norms such as the ISO 26262 in the automotive industry have significantly increased
the demand for safety experts. However, this fast growth has led to many misconceptions and wrong interpretations of functional safety in practice as well
as an in research. This talk therefore starts with an overview on the underlying fundamentals and principles of functional safety, how those concepts are
reflected in current standards such as the ISO 26262, and how they are efficiently applied to assure a system's functional safety. In the second part, the
talk points out current challenges posed by new trends such as the internet of things or autonomous systems. Even though those challenges require some
paradigm shifts in safety assurance and are nontrivial to solve, the capability of efficient safety assurance despite these challenges opens new chances
and will be a key success factor in the upcoming international competition. Therefore, the talk will further show how current state-of-the-art approaches
such as modular safety assurance or runtime safety assurance help solving those challenges.
Robert Bosch - Germany
Driverless-cars: the holy grail of autonomous systems' safety
Future automotive computing platforms are a hub for technology integration. In fact, the driverless car is becoming a holy grail of autonomous systems safety.
This talk paints a picture of the impending functional safety challenges as the automotive sector evolves from advanced driver assistance towards self-driving autonomous cars.
I conclude the talk by giving a link to some of the vital ingredients that help engineers design and test safer cars of the future.
Special Session 2: Test technologies for safety-critical automotive ICs
Moderator: Nilanjan MUKHERJEE, Mentor - A Siemens Business, USA
Intel - Israel
In-system test for automotive SoC
Testing of automotive SoCs brings in many new challenges. The need for high test quality is pushing the industry towards a “0 DPPM” goal for manufacturing test.
At the same time, functional safety requirements as specified in the ISO 26262 standard, describe the need for monitoring SoCs during in-system operation to
improve the reliability and safety of the system. Built-In Self-Test (BIST) is used for testing random logic and memories during key-on/off. In certain cases,
it is also applied periodically during in-system operation to test a particular module when it is functionally inactive. All these requirements call for an
extensive and scalable DFT architecture for the automotive SoC design, providing adequate flexibility to meet the test quality, test cost, and in-system test
ON Semiconductor - USA
Out with the old, in with the new: the quest to oust traditional fault models
For decades, the stuck-at and transition fault models have been the backbone of the test indus-try. Suffering from overuse, this backbone is old and buckling
and substantial physical therapy is needed. This talk addresses such therapy, in the form of improved fault models which have been developed over the past few
years. The ability to generate significantly improved tests is now available, in the form of both static and dynamic critical area-based cell-aware, interconnect
bridging, opens and cell neighbourhoods. Using production results, quantifiable improvements in quality will be demonstrated and the argument presented that
stuck-at and transition are now obsolete models. Further results will be presented that demonstrate that the practice of generating top off static patterns
is wrong and leaves various detectable defects undetected.
Power Integrations - USA
Testing AMS integrated circuits - Progressing Linearly to 0 DPPM
The development of tools and methods for testing analog circuits has progressed slowly compared to those for digital circuits. For today's ever more complex
functionality combined with the increasing need for 0 DPPM, analog test has become a more significant challenge, and at times a constraint. This will be a
discussion of where analog test has progressed recently, and new limitations that challenge IC development and manufacturing.
Special Session 3: Device Aging: Security and Reliability Concerns in Emerging Technologies
Moderator: Naghmeh KARIMI, University of Maryland - USA
Delft University - The Netherlands
Degradation analysis of high performance industrial FinFET SRAMs
This presentation focuses on the degradation analysis of an industrial high performance 14nm Fin-FET memory. It presents not only the relative degradation of
each individual memory component for different applications, but also the impact of the interaction between these components and their overall effect on the
whole memory aging.
Georgia Institute of Technology - USA
Ensuring the reliability of digital fingerprints and random numbers extracted from CMOS SRAMs as the device ages
While digital identifiers, PUFs, and true random number generators (TRNGs) based on the random power up states of SRAM cells have long been investigated, they
have so far not proven practical because of instability in the individual SRAM cells from stress and aging. We present a novel methodology that uses controlled
BTI stress to effectively neutralize changes in the power up bias in the SRAM cells and thereby achieve robust and reliable operation of these key security
University of Stuttgart - Germany
Secure aging monitoring
Aging detection, protection and prevention schemes may introduce additional security threats. This talk deals with the connection between reliability and security
infrastructures, and discusses the three main classes of aging detection and prevention schemes including workload monitoring, circuit monitoring and periodic
University of Maryland - USA
Revisiting device security regarding aging
Due to device aging, the delay and power consumption of the transistors embedded in an integrated circuit changes over time. This in turn, affects the
success of the attacks built upon exploiting unintentional leakages from the device such as its power consumption or timing characteristics to leak sensitive
information from the device. This presentation focusses on the effect of aging from security perspective and presents the cases where aging positively/negatively